Multi-modal analog multiplexed data acquisition systems are a category of data acquisition systems that employ at least one shared analog to digital converter (ADC) and additional circuit elements to sample the voltage levels of multiple individual analog signals with significantly dissimilar characteristics, and convert the sampled voltage levels to digital representations. In contrast to multi-modal systems, an analog multiplexed data acquisition system that is not multi-modal samples multiple analog signals with similar characteristics. In other systems, the analog to digital data conversion is done for each sensor, and no multiplexing is used.
Typically the several input analog signals of a multi-modal analog multiplexed data acquisition system have a variety of differing characteristics such as signal bandwidth, range of voltage levels, and noise content.
A multi-modal analog multiplexed system as well as other types of data acquisition systems may employ circuitry to adjust the voltage range of the input analog signals, filter high frequency components, and perform other signal conditioning and processing functions necessary to meet system requirements for a specific application. For simplicity of explanation, the term “input analog signal” refers both to an analog signal after modification as well as the signal itself for unmodified signals.
Typical multi-modal analog multiplexed systems couple multiple input analog signals to the inputs of an analog multiplexer. The single output of the analog multiplexer is coupled to the input of a sample and hold circuit. The output of the sample and hold circuit is coupled to the input of the ADC conversion circuitry. The sample and hold circuit is often internal to modern ADC integrated circuits.
An example of a multi-modal analog multiplexed system is a health and fitness product configured to assist a user in managing physical exercise routines by providing data sensed from their body during exercise. Such an example system could employ different types of analog sensors for measuring human body parameters such as pulse rate, galvanic skin response and heart electrical activity (similar to an electrocardiogram). Other applications would include systems with a variety of sensors, for example sensors could measure temperature, air or fluid pressure, humidity, luminance, proximity, received signal strength, and the like.
The function of the sample and hold circuit of a multi-modal analog multiplexed system is to briefly store the voltage level of the input analog signal that has been routed from one of the multiplexer inputs to the multiplexer output. The voltage level stored is approximately equal to or approximately proportional to the instantaneous voltage of the input analog signal at the point in time when the sample is taken.
In prior known approach systems, in a typical multi-modal analog multiplexed system, sampling the analog input signal and then performing analog to digital conversion are performed as two separate events. To accomplish this it is necessary to store the sampled input signal on a sampling capacitor, and then to consequently to introduce a buffer to transfer the stored voltage from the sampling capacitor to a second capacitor within the analog to digital converter (ADC). A buffer between the sampling capacitor is used and has the responsibility for quickly charging the second capacitor within the ADC (which requires high bandwidth) and without adding excess noise to the sampled signal (which require low noise) and at low power consumption.
The parameters and requirements on the prior known approach systems lead to design trade-offs. The conventional design trade-offs are first, using a low bandwidth, high noise power spectral density amplifier, which can be designed to operate at low power. The total noise (Noise power spectral density multiplied by bandwidth) can be low, but only if the bandwidth is low too. So the noise power spectral density is high, and bandwidth is low. Second, the use of a high bandwidth, high noise power spectral density amplifier can be considered, which can be designed to operate at a moderate power. Third, the use of a high bandwidth, very low noise spectral power density amplifier can be considered, which meets the requirements for bandwidth and low noise but cannot be designed for low power.
Many ADC systems employ a balanced circuit path for differential analog signals. For simplicity of explanation a single-ended (not balanced) system will be described herein; however, the descriptions herein of both prior approaches and the arrangements of the present application are applicable to circuits with balanced topologies as well as single-ended topologies.
A commonly employed prior known approach single-ended sample and hold circuit couples the output of the analog multiplexer to the input of a buffer (an amplifier to provide current drive typically with a gain of 1). The buffer output is coupled to the input of a low loss switch such as a field effect transistor (FET). The output of the switch is coupled to both the input of the ADC conversion circuitry and one terminal of a capacitor (referenced herein as the sampling capacitor). The other terminal of the sampling capacitor is typically connected to a known reference potential, such as ground of the ADC reference voltage circuit. In the case of some prior approaches the above buffer may not be described as part of the sample and hold circuit. (As stated above the ADC may contain the switch and sampling capacitor.) Sample and hold circuits can potentially be more complex than the single switch and single capacitor described above. The descriptions herein of sample and hold circuits for prior approaches and the present application are based on a single switch and single capacitor as described above, but the concepts presented herein are applicable to more complex sample and hold circuit topologies that are functionally equivalent to the above described sample and hold circuit with a single switch and single capacitor.
FIG. 1 depicts, for example, a prior known approach for a multi-modal analog multiplexed system 100. In FIG. 1, a plurality of sensors 102 such as photodiodes, capacitive sensors, thermocouples, and the like are shown. A plurality of n buffers 1014 are shown coupled to n sampling capacitors 109 using n sampling switches 106 to form the samples across the sampling capacitors Cs. A shared output buffer 103 is shown coupled by n output switches 108 to the sampling capacitors Cs. The output buffer and the output switches and the node 110 form a multiplexer to route a single sample to the analog to digital converter ADC 107.
The operation of the example sample and hold circuit arrangement 100 to acquire a sample of the approximate instantaneous input analog signal voltage begins with the particular switch 106, corresponding to a selected input signal, transitioning from a blocking state (off) to a low loss conducting state (turning on). Turning on the switch 106 couples the selected buffer 104 output to the selected sampling capacitor Cs 109, and to the ADC conversion circuit input (the ADC conversion circuit is inactive at this time). The capacitor Cs charges (or discharges) in series with the buffer 104 output impedance, with the voltage across the sampling capacitor Cs approaching the voltage of the input analog signal. For simplicity of explanation, the descriptions herein of the sample and hold circuit including the buffer are based on an ideal RC (resistive-capacitive) circuit and ideal switch; however, non-ideal circuits can be made to operate similarly. After a pre-defined sampling time the switch 106 turned off. The sampling switch 108 then turns on coupling the capacitor to the buffer 103, and the ADC 107 then begins the process of converting the voltage across the sampling capacitor to a digital representation. This process is continued for each of the analog input signals.
A key characteristic of the sample and hold circuit such as shown in arrangement 100 is the bandwidth, which is related to the time required for the sampling capacitor to charge to a pre-defined fraction of a step voltage input when the switch 106 described above turns on. For an ideal circuit response to a step voltage input, the voltage across the capacitor reaches 1−e−t/RC, where t is the amount of time in seconds after the step input is applied across the resistance, R and the capacitance, C. R is the resistance in ohms in series with the sampling capacitor, and C is the capacitance in farads of the sampling capacitor. For the case of the sample and hold circuit, the resistance R is the output impedance of the buffer summed with intrinsic resistance of the circuit including resistance of interconnect conductors and internal resistance of the capacitor.
The product of R and C is known as the time constant (referred to as “tau” or “τ”). The charge across the capacitor of an ideal circuit of a resistor and capacitor in series reaches approximately 63.2% of the step input voltage after one time constant (obtained by evaluating the expression 1−e−t/τ with τ=t).
For a given prior known approach sample and hold circuit, a performance requirement typically exists for the voltage across the sampling capacitor to reach a pre-defined fraction of the instantaneous input analog signal voltage during the period of time the sample and hold switch is turned on, as described above. For example, for a case where the pre-defined fraction is 0.9999, the equation 0.9999=1−e−t/τ can be solved for the minimum number of time constants comprised by the sampling period (the time that the sample and hold switch is turned on). In a typical example, the minimum number of time constants can be approximately 9.2. The pre-defined fraction of the instantaneous input voltage is typically based on the number of digital bits of resolution produced by the ADC.
The settling time parameter of the sample and hold circuit is the time required for the voltage across the sampling capacitor to reach the predefined fraction of a step input voltage. Prior approach circuits are typically arranged and operated such that the sampling period and the settling time are approximately equivalent.
The bandwidth of the sample and hold circuit is inversely proportional to the time constant τ. The above described sample and hold circuit forms an RC low pass filter where the sampling capacitor is in series with the buffer output impedance and the previously described intrinsic resistances of other circuit elements. The bandwidth of an ideal RC low pass filter is often defined as the frequency at which the square of the output voltage of the filter (the voltage across the capacitor) is equivalent to one-half the square of the input voltage of the filter for a single frequency sine-wave input. Based on the above definition the bandwidth of an ideal RC low pass filter is ½πτ (in Hz.)
Various ADC technologies exist. The selection of a specific ADC technology for a given multi-modal analog multiplexed system is typically based on a number of factors including, for example, circuit cost, size, power consumption, resolution, and the number of conversions per second that can be achieved. The descriptions of prior approach and present application multi-modal analog multiplexed systems herein are applicable to systems employing ADC technologies that require a sample and hold circuit employing capacitance for voltage sampling and storage whether the sample and hold circuit is internal to the ADC, or the sampling capacitor can be implemented external to the ADC.
The number of samples per second that can be converted to digital representation by prior approach multi-modal analog multiplexed systems is typically based primarily on the sum of sampling period (of the sample and hold circuit) and the conversion time of the ADC. The reciprocal of the sum of the sampling period, the ADC conversion time, and other delays in the system is the maximum sample rate in samples per second that can be achieved by prior approaches.
Therefore, for prior known approach multi-modal analog multiplexed systems, an interdependence exists among the key characteristics of bandwidth of the sample and hold circuit, including the sample rate of the system, noise contribution to the sampled voltage level, and power consumption.
Multiplexing of the input analog signals is typically performed such that each input analog signal is selected one signal at a time by the multiplexer in a pre-defined sequence and for a pre-defined period of time that is approximately the same period of time that each of the other input analog signals are selected. The multiplexer is typically controlled such that the selection of input analog signals in a pre-defined sequence repeats cyclically while the system is operating. When an input analog signal is selected by the multiplexer, the selected signal is routed through the multiplexer to the multiplexer output and all other input analog signals are blocked. The digital information can then be used for further computation, for display, for transmission to another system or computer, and the like.
High bandwidth (compared to low bandwidth) for the sample and hold circuit typically results in higher sample rates being possible, but also in increased noise contribution to the sampled voltage. A high sample rate compared to a low sample rate could result in the system having the capability to be made with a larger number of input analog input signals.
In contrast, a sample and hold circuit made with low bandwidth typically results in lower sample rate, but also having a reduced noise contribution to sampled voltage. However, a low sample rate may not allow system requirements of the number of input analog input signals to be met.
Improvements are thus desirable in the performance and efficiency of multi-modal analog multiplexed systems. Improvements that result in both higher sample rates and reduction of noise contribution to the sampled voltage, without significant increases in power consumption or circuit complexity, are of particular importance.